The present invention relates in general to semiconductor technology and in particular to high-voltage semiconductor structures and methods of manufacturing the same.
FIG. 1 shows a cross-section view of a portion of a conventional power MOSFET having a buried-gate structure. A highly-doped substrate 102 forms the drain contact for MOSFET 100. An epitaxial layer 104 formed over substrate 102 includes source regions 124a,b formed in body regions 108a,b. Body regions 108a,b are flanked on one side by gate trench 119. P+ regions 126a,b form the areas through which contact is made to body regions 108a,b. Gate trench 119 is filled with polysilicon forming the MOSFET gate 118. When MOSFET 100 is turned on, current travels in a vertical direction from source regions 124a,b along a channel parallel to the sidewalls of gate trench 119 to the backside drain.
FIG. 2 shows a cross-section view of a conventional MOSFET 200 with planar gate structure. A highly doped substrate 202 forms the drain contact for MOSFET 200. An epitaxial layer 204 formed over substrate 202 includes source regions 224a,b formed in body regions 208a,b. P+ regions 226a,b form the areas through which contact is made to body regions 208a,b. The MOSFET gate 218 is formed on top of the silicon surface instead of being recessed in a trench. When MOSFET 200 is turned on, current flows from source regions 224a,b along a channel beneath gate 118 and then vertically through drift region 206 to the backside drain.
The structures shown in FIGS. 1 and 2 are typically repeated many times to form an array of cells. The array may be configured in various cellular or stripe layouts known to one skilled in this art. These and other types of power devices have long been known. Recent advances in semiconductor manufacturing have increased the density (i.e., the number of cells in a given silicon area) of devices. However, the higher density does not necessarily improve power loss in mid to high voltage range (e.g., 60 to 2000 volts) devices. In such devices, the power loss is primarily due to the high resistivity of the drift region (e.g., region 106 in FIG. 1). Drift regions have high resistivity because in order for the device to sustain the high voltages during the blocking state, the drift region is lightly doped. The high resistivity of the drift region results in a higher on-resistance, which in turn results in high power loss. Since a high blocking voltage is a critical feature for mid to high voltage power devices, increasing the drift region doping is not an option. Similar issues are present in power diode devices.
Attempts have been made to improve the device power loss while maintaining a high blocking voltage. In one approach, columnar opposite polarity regions extending parallel to the current flow are formed between the body-gate structure at the top and the substrate at the bottom. The columnar opposite polarity regions prevent the electric field from decreasing linearly away from the base-drift junction, thus allowing the device to support higher blocking voltages. This technique however depends on charge balance between the conduction and opposite polarity regions and thus requires precise doping control of the opposite polarity regions. The opposite polarity regions are formed before the diffused base and source regions. When the base and source regions are annealed during a thermal cycle, the dopants in the opposite polarity regions undesirably diffuse into each other. This dopant inter-diffusion makes the thermal processing difficult and limits shrinking of the cell pitch. The inability to shrink the cell pitch is specially problematic in mid to low voltage devices in which the power loss occurs primarily in the channel region rather than in the drift region. In the mid to low voltage devices, the power loss in the channel region is typically countered by making the cell pitch as small as possible so that a large number of cells can be formed in the same silicon area. The columnar opposite polarity regions technique is thus unattractive for mid to low voltage devices as it can not be shrunk.
Thus, a technique which enables achieving a high device blocking capability, low on-resistance, and high current handling capability without preventing the cell pitch to be shrunk is desirable.